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IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
CS[1:0] = 10:
transmits data on falling edges of BCLK, receives data on falling edges of BCLK.
CS[1:0] = 11:
transmits data on falling edges of BCLK, receives data on rising edges of BCLK.
The PCM data Offset Configuration bits (OC[2:0]) determine that the transmit and receive time slots of PCM data offset from the FS
signal by how many periods of BCLK:
OC[2:0] = 000:
0 period of BCLK (default);
OC[2:0] = 001:
1 period of BCLK;
OC[2:0] = 010:
2 periods of BCLK;
OC[2:0] = 011:
3 periods of BCLK;
OC[2:0] = 100:
4 periods of BCLK;
OC[2:0] = 101:
5 periods of BCLK;
OC[2:0] = 110:
6 periods of BCLK;
OC[2:0] = 111:
7 periods of BCLK.
GREG8: SLIC Ring Trip Setting and Control, Read/Write (27H/A7H)
The Output Polarity Indicator bit (OPI) indicates the valid polarity of output:
OPI = 0:
the selected output pin changes from low to high to activate the ring (default);
OPI = 1:
the selected output pin changes from high to low to activate the ring.
The Input Polarity Indicator bit (IPI) indicates the valid polarity of input:
IPI = 0:
active low (default);
IPI = 1:
active high.
The Input Selection bit (IS) determines which input will be selected as the off-hook indication signal source.
IS = 0:
SI1 is selected (default);
IS = 1:
SI2 is selected.
The Ring Trip Enable bit (RTE) enables or disables the ring trip function block:
RTE = 0:
the ring trip function block is disabled (default);
RTE = 1:
the ring trip function block is enabled.
The Output Selection bits (OS[2:0]) determine which output will be selected as the ring control signal source.
OS[2:0] = 000 - 010:
not defined;
OS[2:0] = 011:
SB1 is selected (when SB1 is configured as an output);
OS[2:0] = 100:
SB2 is selected (when SB2 is configured as an output);
OS[2:0] = 101:
SB3 is selected (when SB3 is configured as an output);
OS[2:0] = 110:
SO1 is selected;
OS[2:0] = 111:
SO2 is selected.
GREG9: SI Data, Read Only (28H)
The SIA[3:0] bits contain the debounced data (off-hook status) on the SI1 pins of Channel 4 to Channel 1 respectively.
The SIB[3:0] bits contain the debounced data (ground key status) on the SI2 pins of Channel 4 to Channel 1 respectively.
b7
b6
b5
b4
b3
b2
b1
b0
Command
R/W
0
1001
11
I/O data
OPI
Reserved
IPI
IS
RTE
OS[2]
OS[1]
OS[0]
b7
b6
b5
b4
b3
b2
b1
b0
Command
00
1010
00
I/O data
SIB[3]
SIB[2]
SIB[1]
SIB[0]
SIA[3]
SIA[2]
SIA[1]
SIA[0]
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